1. Field of the Invention
This invention relates to a voltage regulator which allows the terminals of a memory cell to be suitably biased. More particularly, the invention is concerned with a voltage regulator for programming non-volatile memory cells.
2. Discussion of the Related Art
In a well-known manner, a non-volatile memory cell comprises a MOS transistor having a "floating" gate terminal, that is exhibiting a high DC impedance to all the other terminals of the cell and the circuit in which the cell is connected. The cell also has a second electrode, known as the control gate electrode, which is driven by appropriate control voltages. The other electrodes of the MOS transistor are the usual drain, source and body terminals.
By changing the value of the voltage applied to the control gate, the amount of the charge present in the floating gate can be changed. Thus, the transistor can be placed in either of two logic states: a first state with a "high" threshold voltage, and a second state with a "low" threshold voltage.
By applying a voltage in between these two values to the control gate, the state of the transistor can be "read", since the transistor will either present a low or a high impedance between its drain and source terminals according to the value of the threshold voltage. The transistor functions, therefore, as a logic storage element.
Furthermore, since the floating gate presents a high impedance to any other terminals of the cell, the charge stored in the transistor can be held for an indefinite length of time, even if the power supply to the circuit in which it is connected is removed. Thus, the cell has non-volatile memory characteristics.
The operation whereby charge is stored in the floating gate is referred to as the cell "programming", whereas the operation whereby said charge is removed from the floating gate is referred to as the cell "erasing".
A non-volatile memory circuit integrated to a semiconductor usually includes a very large number of such cells. The cells are laid in rows (word lines) and columns (bit lines). The cells in one row share the line which drives their respective control gates. The cells in the same bit line share the drain electrode. In order to program a given cell, the appropriate positive voltage values are impressed on the word line and the bit line that locate it.
A memory cell programming is strongly affected by the voltage applied to the drain terminal, that is the voltage VP present on the bit line to which it belongs.
Also known is that with non-volatile memory cells, in particular of the flash type, a reduced value of said drain voltage VP gives rise to insufficient and slow cell programming, whereas an excessively large value results in the cell being partially erased (the so-called "soft erasing" phenomenon). Thus, the optimum range for VP is fairly narrow, typically between about 5 and 6 V.
In view of the foregoing, the memory circuit should be provided with a particularly sophisticated and accurate voltage regulator to supply the bit line with the appropriate voltage during the programming step.
One of the methods employed to program memory cells utilizes the phenomenon of the injection of hot electrons through the gate oxide of the cell.
For the injection process to be triggered, it is necessary that the cell terminals be suitably polarized; the drain-source voltage should attain a value in the 5 to 6 volts range, in order to accelerate the electrons present in the channel, while the gate-source voltage should be a value of about 12 volts, so as to attract the accelerated electrons.
However, as previously mentioned, what is critical is the value of the drain voltage VP, and this should be held as stable as possible during the programming.
The fluctuations in said voltage are tied to the following factors:
technological changes in the manufacturing processes of the various components; PA1 increased threshold voltage of the cell during the programming, and consequent decrease in current draw; and, PA1 voltage drops across the selection transistors present in the bit lines. PA1 the bias current drawn by the MOS M9, shown in FIG. 1, is carried over to the drop resistance to cause an undesired constant component to appear in the compensation voltage Vcomp. This constant voltage component is particularly objectionable where a single cell is programmed, because in this case, the current drawn by the transistor M9 is then no longer negligible against that required for the programming; and PA1 while the cells are being read, the bit line is polarized to a voltage of about 1 V, and connected to the line VP via a p-channel MOS transistor. This transistor has its gate voltage Vg0=0 V (as impressed by a switch being also supplied VP) and its source voltage Vs0=1 V, and is therefore in conduction.
The last-mentioned is a significant effect especially with large capacity memories, wherein in view of the small dimensions involved, the selection transistors have a particularly small W/L (channel width to length) ratio and, therefore, high series resistance.
Thus, there evidently exists a need for a voltage regulator of sufficiently refined design to take account of all the factors involved. The prior art solves these problems by providing a circuit wherein the output voltage from the regulator exceeds that sought for the bit line by an appropriate amount which is continually dependent on the actual current flowing through the selection transistors in the bit line.
To accomplish this, a polarization technique of the adaptive type is employed which provides for a positive feedback structure.
An example of this prior approach is shown schematically in FIG. 1. In essence, a voltage generator generates a constant voltage (VPROG) equal to the voltage that should appear on the selected bit line if optimum programming conditions are to be provided. That voltage is added a varying voltage, designated Vcomp. The value Vcomp is obtained by mirroring the current supplied from the regulator to the bit line on elements which are mirror-images of the bit line selection transistors, thereby producing the same voltage drop across them.
More specifically, the regulated voltage is supplied from a source-follower MOS transistor, designated MOUT, which is driven by a suitably fed-back operational amplifier (4). This arrangement includes two feedback loops: a first loop inherent to the voltage regulator, and the second loop (comprising a MOS transistor, designated MPR2, and a generic block H) to compensate for the voltage drop at the bit line. The second loop supplies a current to a drop resistance Rdrop which is proportional to the current from the regulator, and hence, tied to that drawn by the cell being programed.
In a storage device, the programming usually takes place in parallel through all the cells of one word; of course, only those cells in which a voltage rise is to occur, i.e. which are to contain a logic "1", would be actually programed.
The current drawn from the bit line at the programming stage will depend, therefore, on the pattern of bits to be stored. To avoid altering the compensation, the drop resistance should be varied accordingly.
However, this prior approach has some drawbacks, as follows:
At the reading stage, the programming voltage VP is zero and the p-channel MOS transistor connects the capacitance associated with the junction of the conducting transistor MOUT to the bit line; as a result, the capacitance of the bit line is greatly increased and its reading speed greatly decreased. This is a baffling phenomenon in that it only comes out where the bit line takes a higher voltage than the p-channel threshold voltage; this may happen when the supply voltage exceeds its rated value. Accordingly, this phenomenon should be carefully suppressed.
It is one object of the present invention to provide a voltage regulator which can supply the voltage actually needed for proper programming, but also hold the programming line and bit line decoupled while the latter is being read.